Memory device for reducing a write fail, a system including the same, and a method thereof

ABSTRACT

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No. 14/013,275filed Aug. 29, 2013, which claims priority under 35 U.S.C. §119(a) toKorean Patent Application No. 10-2012-0095223 filed on Aug. 29, 2012 inthe Korean Intellectual Property Office, the disclosure of which isincorporated by reference herein in its entirety.

TECHNICAL FIELD

The present inventive concept relates to a memory device, and moreparticularly, to a method of writing data to a memory device.

DISCUSSION OF RELATED ARTS

The increased degree of integration of semiconductor devices has reducedelements in size and a gap between elements. For example, dynamic randomaccess memory (DRAM) device decreases in size, contact resistance andbit line resistance of a DRAM write path, thereby increasing a writetime through the DRAM write path. Further, as the size of celltransistors is reduced to increase the degree of integration ofsemiconductor devices, the driving performance of the cell transistorsdecreases. Accordingly, semiconductor devices may need more time for awrite operation.

SUMMARY

According to an exemplary embodiment of the inventive concept, a memorysystem includes a memory device and a memory controller. The memorydevice includes a plurality of memory cells. The memory controller isconfigured to continuously perform a plurality of write commands on thememory device. In the memory system, the memory device perfoms a firstwrite operation corresponding to a last write command of the pluralityof write commands, performs a precharge operation and then performs asecond write operation corresponding to the last write command after theprecharge operation.The first write operation and the second writeoperation write a same data to memory cells of plurality of memory cellshaving a same address.

The precharge operation may be performed in response to a prechargecommand issued from the memory controller or an internally generatedprecharge command in the memory device.

According to an exemplary embodiment of the inventive concept, a methodof writing data to a memory device is provided. A word line in a memorybank is activated in response to an active command. A plurality of datasets is continuously written to memory cells associated with the wordline in response to a corresponding write command of a plurality ofwrite commands. The word line is precharged after a last write commandof the plurality of write commands is performed. In response to the lastwrite command, the last data set is written to the memory cells afterthe precharging.

The precharging maybe performed in response to a precharge commandissued from a memory controller or an internally generated prechargecommand in the memory device.

According to an exemplary embodiment of the inventive concept, a methodof writing data to a memory device is provided. A plurality of writerequests and a plurality of data sets are received from a host. Asequence of a plurality of write commands from the plurality of writerequests is generated according to a predetermined scheduling method andthe sequence is applied to a memory device between an active command anda precharge command. A last write command of the plurality of writecommands is applied to the memory device after the precharge command.

According to an exemplary embodiment of the inventive concept, a memorycontroller includes an arbiter. The arbiter is configured to generate anactive command, a precharge command, and a plurality of write commandshaving a common row address and configured to continuously issue theplurality of write commands between the active command and the prechargecommand, wherein the precharge command is issued after a first writeoperation is performed in response to a last write command of theplurality of write commands , the last write command is issued for asecond write operation after the precharge command, and wherein thefirst write operation and the second write operation write a same dataset to memory cells of plurality of memory cells having a same columnaddress.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the inventive concept will become moreapparent by describing in detail exemplary embodiments thereof withreference to the accompanying drawings of which:

FIG. 1 is a block diagram of a memory system according to an exemplaryembodiment of the inventive concept;

FIG. 2 is a block diagram of a memory controller according to anexemplary embodiment of the inventive concept;

FIG. 3 is a block diagram of a memory device according to an exemplaryembodiment of the inventive concept;

FIG. 4 is a block diagram of a memory cell illustrated in FIG. 3according to an exemplary embodiment of the inventive concept;

FIG. 5 is a circuit diagram conceptually showing a data write path tothe memory cell illustrated in FIG. 4;

FIG. 6 is a flowchart of a method of writing data to a memory deviceaccording to an exemplary embodiment of the inventive concept;

FIG. 7 is a diagram of a command queue and an execution sequenceaccording to an exemplary embodiment of the inventive concept;

FIGS. 8A and 8B are signal timing charts illustrating a data writeoperation according to an exemplary embodiment of the inventive concept;

FIGS. 9A through 9C are signal timing charts illustrating a data writeoperation according to an exemplary embodiment of the inventive concept;

FIG. 10 is a block diagram of a memory system according to an exemplaryembodiment of the inventive concept;

FIG. 11 is a block diagram of a memory system according to an exemplaryembodiment of the inventive concept;

FIGS. 12A through 12C are diagrams for explaining a method of schedulinga write operation according to an exemplary embodiment of the inventiveconcept;

FIG. 13 is a diagram for explaining a method of scheduling a writeoperation according to an exemplary embodiment of the inventive concept;

FIG. 14 is a block diagram of a module including a plurality of memorydevices according to an exemplary embodiment of the inventive concept;

FIG. 15 is a block diagram of a module including a plurality of memorydevices according to an exemplary embodiment of the inventive concept;

FIG. 16 is a block diagram of a data processing system including thememory device illustrated in FIG. 1 according to an exemplary embodimentof the inventive concept;

FIG. 17 is a block diagram of a data processing system including thememory device illustrated in FIG. 1 according to an exemplary embodimentof the inventive concept;

FIG. 18 is a block diagram of a data processing system including thememory device illustrated in FIG. 1 according to an exemplary embodimentof the inventive concept;

FIG. 19 is a diagram of a multi-chip package including the semiconductormemory device illustrated in FIG. 1 according to an exemplary embodimentof the inventive concept; and

FIG. 20 is a three-dimensional conceptual diagram of an example of themulti-chip package illustrated in FIG. 19 according to an exemplaryembodiment of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the inventive concept will be described belowin more detail with reference to the accompanying drawings. Thisinventive concept may, however, be embodied in different forms andshould not be construed as limited to the embodiments set forth herein.In the drawings, the size and relative sizes of layers and regions maybe exaggerated for clarity. Like numbers may refer to like elementsthroughout the specification and drawings.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent.

As used herein, the singular “a”, “an” and “the” are intended to includethe plural forms as well, unless the context clearly indicates otherwise

FIG. 1 is a block diagram of a memory system 10 according to anexemplary embodiment of the inventive concept. FIG. 2 is a block diagramof a memory controller 100 according to an exemplary embodiment of theinventive concept. FIG. 3 is a block diagram of a memory device 200according to an exemplary embodiment of the inventive concept. Referringto FIGS. 1 through 3, the memory system 10 includes the memorycontroller 100 and the memory device 200.

The memory controller 100 includes an arbiter 110, a command queue, atransaction processing unit 140, and a memory interface 150. The commandqueue includes a write queue 130 and a read queue 120, as illustrated inFIG. 2. In an exemplary embodiment, the write queue 130 and the readqueue 120 may be integrated into a single queue.

The arbiter 110 receives a write request and a read request andgenerates a write command from the write request and a read command fromthe read request, sequentially storing the read command to the readqueue 120 and the write command to the write queue 130. The read queue120 may store a read command and an address. The write queue 130 maystore a write command, an address, and write data. In an exemplaryembodiment, the write data may be stored in a memory (e.g., a data queueor buffer (not shown)) while the write command and the address arestored in the write queue 130.

The arbiter 100 schedules or re-orders the sequence of the read and/orwrite commands stored in the queues 120 and 130 according to apredetermined scheduling algorithm and stores the commands.

The memory controller 100 generates and executes other commands tocontrol the operations of the memory device 200. For instance, when thememory device 200 includes a DRAM device, the arbiter 110 also generatesan active command and a precharge command to open and close each row toexecute a read or write request from the host. The arbiter 110 schedulescommands from the requests received from the host 20 and the active andprecharge commands according to a predetermined scheduling method. Thearbiter 110 transmits the commands including an active command, aread/write command, and a precharge command according to the schedulingmethod to the memory device 200 via the memory interface 150 to controlthe operations of the memory device 200.

The transaction processing unit 140 prepares the memory device 200 toexecute the commands CMD output from the arbiter 110. The transactionprocessing unit 140 may serve to provide data to the host 20 withoutaccessing the memory device 200. For example, when receiving a readrequest from the host 20 with respect to write data that has been storedin the write queue 130, in other words, write data that has not beenwritten to the memory device 200, the memory controller 100 may read thedata from the write queue 130 and transmit it to the host 20 withoutaccessing the memory device 200.

The memory controller 100 may execute a read command prior to any othercommands before a write command among multiple read or write requestsreceived from the host 20. The memory controller 100 stores a writecommand in the write queue 130 and then schedules an execution sequenceof commands stored in the write queue 130 according to a predeterminedscheduling method. For example, a write command stored in the writequeue 130 may be executed according to the priority determined by thescheduling method of the memory controller 100 and then the writecommand may be erased from the write queue 130.

A pointer designating a write command entry in the write queue 130 maybe sequentially increased. For instance, once a write command designatedby a pointer in the write queue 130 is executed, the pointer may beshifted to a next write command entry. However, after a write command(e.g., a write command right before a precharge command) is executed ata last write cycle in which a write recovery time (tWR in FIGS. 8A and9B) is not sufficient, the memory controller 100 does not shift thepointer to a next entry but controls the write command to be executedagain. For example, when a write command entry corresponds to datawritten right before the precharge of the memory device 200 and thememory controller does not have sufficient time to write the data, thememory controller 100 re-executes the write command by retaining thewrite command entry in the write queue 130 instead of erasing it afterthe write command corresponding to the entry is executed. In anexemplary embodiment, the memory controller 100 may execute the writecommand entry after execution of any other command following theprecharge. The precharge may be performed in response to a prechargecommand issued from the memory controller 100 or an internally generatedprecharge command in the memory device 200. For example, anauto-precharge operaion may be performed by an internally generatedprecharge command without a precharge command issued from the memorycontroller 100.

The memory device 200 includes a memory cell array 210, a row decoder220, a sense amplifier 230, a column decoder 240, a control logic 250,and a data input/output circuit 260. The operations of the memory device200 will be described later.

The memory cell array 210 is a data storage area in which memory cellsare arranged in a row direction and a column direction. The senseamplifier 230 senses and amplifies data in the memory cells and storesdata in the memory cells. The memory cell array 210 illustrated in FIG.3 may include a plurality of (e.g., 4 or 8) memory banks, but theinventive concept is not restricted to the 4 or 8 memory banks.

Data DQ, input through the data input/output circuit 260, is written tothe memory cell array 210 based on an address signal ADD. The data DQread from the memory cell array 210 based on the address signal ADD isoutput through the data input/output circuit 260.

The address signal ADD is input to an address buffer (not shown) todesignate a memory cell to or from which data will be written or read.The address buffer temporarily stores the address signal ADD.

The row decoder 220 decodes a row address in the address signal ADDoutput from the address buffer to designate a word line connected to amemory cell to or from which data will be input or output. For example,the row decoder 220 decodes a row address output from the address bufferand enables a word line in a data write or read mode.

The column decoder 240 decodes a column address in the address signalADD output from the address buffer to designate a bit line connected toa memory cell to or from which data will be input or output.

The memory cell array 210 outputs data from or writes data to a memorycell designated by a row address and a column address.

The control logic 250 receives and decodes an external command signalCMD, and generates a decoded command signal. The control logic 250 mayinclude a mode register set/extended mode register set (MRS/EMRS)circuit (not shown) which sets an operation mode. The MRS/EMRS circuitsets an internal mode register in response to an MRS/EMRS command forsetting the operation mode of the memory device 200 and/or the addresssignal ADD.

Although not shown in FIG. 3, the memory device 200 may also include aclock circuit that generates a clock signal and a power circuit thatreceives an external power supply voltage and generates or distributesan internal voltage.

FIG. 4 is a block diagram of a memory cell 210 according to an exemplaryembodiment of the inventive concept. Referring to FIG. 4, the memorycell 210 includes an access transistor TA connected to a word line WLand a bit line BL and a memory cell MC selectively connected by theaccess transistor TA to the bit line BL. The memory cell MC may includea cell capacitor.

FIG. 5 is a circuit diagram showing a data write path to the memory cellMC illustrated in FIG. 4. Referring to FIG. 5, data is written to thememory cell MC through the bit line BL and the access transistor TA.

The data write path includes bit line resistance Rbl of the bit line BLand contact resistance Rc between the access transistor TA and thememory cell (or cell capacitor) MC. As the bit line BL gets finer andlonger, the bit line resistance Rbl increases. As the contact size ofthe memory cell MC decreases, the contact resistance Rc increases.Therefore, current Ids flowing to the memory cell MC through the bitline BL decreases as the degree of integration of the memory cell 210increases. As a result, it takes more time to write data to the memorycell MC through the increased resistance of the data write path. Forexample, the write recovery time (tWR) needs more clock cycles tocorrectly write data in the memory cell 210, which will decrease writeperformance.

FIG. 6 is a flowchart of a method of writing data to the memory device200 according to an exemplary embodiment of the inventive concept.Referring to FIGS. 2, 3, and 6, a write command and write data arereceived from a host in operation S110. The write command is stored inthe write queue 130 and the write data is stored in the data queue inoperation S120. For instance, the write command and an address arestored in the write queue 130. The address may include a bank address, arow address, and a column address.

The memory controller 100 generates a sequence of commands (e.g., anactive command, a write command, and a precharge command) for writingthe data to the memory device 200 and applies the sequence of commandsto the memory device 200 in operation S130. The memory controller 100,after having issued the precharge command, applies the write commandagain to correctly write the data to the memory device 200 in operationS140. Hereafter, the repeated write command is interchangeably used as arewrite command. To rewrite the data written right before the precharge,the memory controller 100 stores the data till the execution of therewrite command. For example, after the execution of the rewrite commandis completed, the memory controller 100 may erase the write command anddata.

FIG. 7 is a diagram of a command queue and an execution sequenceaccording to an exemplary embodiment of the inventive concept. FIGS. 8Aand 8B are signal timing charts illustrating a data write operationaccording to an exemplary embodiment of the inventive concept. Inparticular, FIG. 8 illustrates the burst write operation of double datarate (DDR) DRAM with a clock write latency (CWL) of 5 and a burst length(BL) of 8.

Referring to FIG. 7 and FIGS. 8A and 8B, write commands “write (a, m,n)” and “write (a, m, p)” are sequentially stored in a write queue asshown in table T3. In response to the write command “write (a, m, n)”,data is written to memory cells whose address information includes abank address of “a”, a row address of “m”, and a column address of “n”.In response to the write command “write (a, m, p)”, data is written tomemory cells whose address information includes a bank address of “a”, arow address of “m”, and a column address of “p”.

To execute the write commands (e.g., “write (a, m, n)” and “write (a, m,p)” stored in the write queue), the arbiter 110 generates a sequence ofcommands (or a command sequence) to be applied to the memory device 200.For instance, the arbiter 110 may generate a sequence of commands suchas an active command “Active (a, m)”, a first write command “write (a,m, n)”, a second write command “write (a, m, p)”, and a prechargecommand “Precharge (a)” and apply the sequence of commands to the memorydevice 200 as illustrated in table T4 of FIG. 7.

Referring to FIGS. 8A and 8B, the command sequence (or an executionsequence) generated by the memory controller 100 may be applied to thememory device 200 in the order of an active command Active, a firstwrite command Write1 at T0, a second write command Write2 at T4, and aprecharge command PRE at Tm in synchronization with the clock signalCLK. A no-operation command NOP may be placed between commands (e.g.,between the first write command Write1 and the second write commandWrite2 or the second write command Write2 and the precharge commandPRE).

In response to the active command Active, a corresponding word line WLin a corresponding bank is enabled. Then, the first write command Writelenables a data write path including a corresponding bit line to writedata DQ. Since the clock write latency is 5, the data DQ is written tothe memory device 200 at T5 five clock cycles after the first writecommand Write1 at T0. The data DQ may be written to memory cellsassociated with the word line WL and the bit line BL before theprecharge command PRE is issued at Tm.

In response to the second write command Write2, a data write path isenabled and second burst data Dset2 is written to the memory device 200at T9. When the precharge command PRE is issued before the second burstdata Dset2 is correctly written, the second burst data Dset2 hasinsufficient write recovery time (tWR). The word line WL that has beenenabled is disabled in response to the precharge command PRE. A secondwrite period tD2 of second burst data Dset2 is a time period measuredbetween the first data D0 at T9 and the precharge command PRE at Tm. Afirst write period tD1 of first burst data Dset1 is a time periodmeasured between the first data D0 at T5 and the precharge command PREat Tm. Accordingly, the second write period tD2 is shorter than thefirst write period tDl. For example, time given to write the secondburst data Dset2 is shorter than time given to write the first burstdata Dset1. As a result, the second burst data Dset2 written rightbefore the precharge command PRE may not be properly written due toinsufficient write recovery time (tWR).

For instance, when a bank and a word line in the memory device 200 areactivated or enabled and then, a plurality of write commands arecontinuously applied prior to a precharge command, the last write cyclecorresponding to the last write command of the multiple write commandshas a shorter data write period than that of the preceding write cycles.Therefore, a corresponding data is insufficiently written into a memorycell corresponding to the last write cycle prior to the prechargecommand. According to an exemplary embodiment, the arbiter 110 controlsthe data Dset2 of the last write cycle to be rewritten thereafter (e.g.,after the precharge command). Here, “data in the last cycle” indicatesthe data Dset2 written right before the precharge.

For a write request, data received from the host 20 is temporarilystored in the data queue in the memory controller 100. The datacorresponding to the last write cycle may be insufficiently written inthe memory device 200 when there is insufficient write recovery time forthe data, Therefore, the memory controller 100 does not erase the datafor the last write cycle from the write queue 130 or the data queue butretains the data and rewrites the data to the same address in the memorydevice 200 after the precharge command.

In this operation, the arbiter 110 regenerates the write command “write(a, m, p)” as shown in FIG. 7 and applies the write command to thememory device 200. The active command “active (a, m)” is applied to thememory device 200 first to enable a bank and a word line correspondingto the write command “write (a, m, p)”. For example, the arbiter 110regenerates and applies a sequence of commands “active (a, m)” and“write (a, m, p)” to the memory device 200 to execute the write command“write (a, m, p)” executed right before the precharge, so that therewrite operation is executed as illustrated in FIG. 8B when the writecommand “write (a, m, p)” has insufficient write recovery time (tWR).The operation is performed in order of FIG. 8A and FIG. 8B in timedomain. Although not shown in FIGS. 8A and 8B, other commands (e.g., aread command) may be executed before the rewrite command.

FIGS. 9A through 9C are signal timing charts illustrating a data writingoperation according to an exemplary embodiment of the inventive concept.FIGS. 9A through 9C also illustrate the burst write operation of DDRDRAM with a CWL of 5 and a BL of 8. For example, FIGS. 9A through 9Cshow a case where data is written to a word line WLn, then data is readfrom another word line WLn+1, and then last data is rewritten to theword line WLn.

Referring to FIGS. 9A and 9B, after data Dset1 and Dset2 are written tothe word line WLn, the word line WLn is precharged by a prechargecommand at Tm before the wordline WLn+1 is enabled. The wordline WLn+1is required to be enabled after a row precharge time (tRP). The rowprecharge time (tRP) is the number of clock cycles needed to terminateaccess to the enabled wordline WLn, and open access to the next wordlineWLn+1. After the precharge command for the word line WLn, the word lineWLn+1 is activated and then a read command Read is applied to the wordline WLn+1 after a time tRCD (i.e., the number of cycles from the activecommand to a read/write command). Then, data is read from the word lineWLn+1 a time tAA (i.e., the number of clock cycles from the read commandto first data) after the read command is applied. Therefore, latency ofthe read command executed after the precharge is “tRP+tRCD+tAA”.

After the read command is executed on the word line WLn+1, the dataDset2 that has been written to the word line WLn before the precharge ofthe word line WLn is rewritten as illustrated in FIG. 9C. The operationsare performed in order of FIG. 9A, FIG. 9B, and FIG. 9C in time domain.

FIG. 10 is a block diagram of a memory system according to an exemplaryembodiment of the inventive concept. Referring to FIG. 10, the memorysystem includes a memory controller 100 a and a memory device 200 a. Thememory device 200 a includes a write queue 270. The structure of thememory controller 100 a may be similar to that of the memory controller100 illustrated in FIG. 2. For example, the memory device 200 a includesthe write queue 270 in addition to the structure of the memory device200 illustrated in FIG. 3. FIG. 10 shows a memory device 200 a includingthe write queue 270 for storing a write command and an address and aseparate storage space for storing relevant data.

The memory device 200 a stores write commands received from the memorycontroller 100 a in the write queue 270. The memory device 200 a maysequentially execute the write commands stored in the write queue 270and erase a write command entry that has been executed from the writequeue 270. However, the memory device 200 a may retain a write commandentry for data that has been written right before a precharge commandeven after the execution of the write command entry. For example, whenthe precharge command is issued before the data is correctly writteninto the memory device 200 a, the memory device 200 a retains the writecommand entry for the rewriting of the data after the precharge command.

The memory device 200 a may execute at least one read or write commandafter the precharge command and before the rewriting of the data. Forexample, after the precharge command and before the rewriting of thedata, a different command or operation may be performed.

The memory device 200 a may execute a rewrite command for rewriting thesame data as that written before without intervention of the memorycontroller 100 a. While writing data to a memory cell in response to awrite command stored in the write queue 270, the memory device 200 a maysend a state signal WT indicating “under a write operation” to thememory controller 100 a. The state signal WT is transmitted using aseparate signal line between the memory controller 100 a and the memorydevice 200 a. For example, a special signal line for the state signal WTis provided between the memory controller 100 a and the memory device200 a. Alternatively, the state signal WT may be transmitted using oneof the existing signal lines. The memory controller 100 a accesses thememory device 200 a based on the state signal WT output from the memorydevice 200 a.

FIG. 11 is a block diagram of a memory system according to an exemplaryembodiment of the inventive concept. Referring to FIG. 11, the memorysystem includes a memory controller 100 b and a memory device 200 b. Thememory device 200 b includes an event detector 280. The structure of thememory controller 100 b may be similar to that of the memory controller100 illustrated in FIG. 2. For example, the memory device 200 b includesthe event detector 280 in addition to the structure of the memory device200 illustrated in FIG. 3.

The event detector 280 detects whether a precharge command is performedon a page after a write command is executed on the page. Hereafter, thepage is interchangeably used as an enabled wordline. At this time, theevent detector 280 sends an alarm signal AT to the memory controller 100b. The alarm signal AT informs the memory controller 100 b that thewrite command has not been properly executed. Upon receiving the alarmsignal AT from the memory device 200 b, the memory controller 100 bconsiders that an operation (e.g., a write operation right beforeprecharge) corresponding to the alarm signal AT has not been performedand performs the operation thereafter.

According to the embodiment illustrated in FIG. 11, the memorycontroller 100 b may apply a rewrite command to the memory device 200 bin response to the alarm signal AT received from the memory device 200 bso that relevant data is rewritten.

The alarm signal AT is transmitted using a separate signal line betweenthe memory controller 100 b and the memory device 200 b. For example, aspecial signal line for the alarm signal AT is provided between thememory controller 100 b and the memory device 200 b. Alternatively, thealarm signal AT may be transmitted using one of the existing signallines.

FIGS. 12A through 12C are diagrams for explaining a method of schedulinga write operation according to an exemplary embodiment of the inventiveconcept. According to an exemplary embodiment, a memory system scheduleswrite operations using a write queue to reduce the number of active andprecharge commands and improve performance of a memory system.

A write queue may be included within the memory controller 100 or thememory device 200, as described above. It is assumed that there arewrite commands A through H as shown in FIG. 12A. As shown in FIG. 12A,each of the write commands A through H includes a bank address BA, a rowaddress RA and a column address CA. Each of the write commands A throughH is for writing data to a certain address.

When the write commands A through H are stored in the write queue, thememory controller 100 may schedule them so that they are sequentiallyexecuted as shown in FIG. 12B.

Alternatively, the memory controller 100 may schedule them referring toaddress information as shown in FIG. 12C. For instance, the writecommands A through H may be scheduled so that write commands having thesame row address RA may be executed sequentially. Referring to FIG. 12C,after the write command A is executed, the write commands C, E, and Ghaving the same row address RA as the write command A may be scheduledto be sequentially executed. Thereafter, the write command B is executedand then write commands D, F, and H having the same row address RA asthe write command B may be scheduled to be sequentially executed.

In FIGS. 12B and 12C, tRP denotes a precharge command period or aprecharge-to-active delay, tRRD denotes an active-to-active commandperiod, tAA denotes an internal read command-to-first data delay, tCCDdenotes a write-to-write delay, and tRCD denotes an active-to-internalread delay or an active-to-write delay.

As illustrated in FIGS. 12B and 12C, a total execution time is muchlonger in a case shown in FIG. 12B than in a case shown in FIG. 12C.Consequently, the total execution time can be reduced by the schedule ofa plurality of write commands.

FIG. 13 is a diagram for explaining a method of scheduling a writeoperation according to an exemplary embodiment of the inventive concept.According to an exemplary embodiment, write commands having the samebank address BA and the same row address RA are sequentially executed.When no addresses include the same bank address BA and the same rowaddress RA, write commands having the same bank address BA aresequentially executed.

When the operations of a memory device (e.g., DRAM) are scheduledaccording to the above-described priority, a case where write commandshaving the same bank address BA but different row addresses RA aresequentially executed may be prevented. As a result, the deteriorationof system performance is prevented.

FIG. 14 is a block diagram of a module 500 including a plurality ofmemory devices 550-1 through 550-4 according to an exemplary embodimentof the inventive concept. Referring to FIG. 14, the module 500 includesa memory controller 510, an input/output (IO) interface 511, and thememory devices 550-1 through 550-4. The memory controller 510 and the I0interface 511 are disposed between a host and the memory devices 550-1through 550-4, communicating with the host.

In an exemplary embodiment, the memory controller 510 and the IOinterface 511 may be integrated in a single chip. Each of the memorydevices 550-1 through 550-4 may communicate data with the host throughthe integrated chip.

The IO interface 511 may include an optical interface. In this case, theIO interface 511 may include an IO controller (not shown) controllingthe input and output operations of the memory devices 550-1 through550-4 and a signal converter (not shown) converting an input or outputsignal into an optical signal.

The IO interface 511 may transfer data using an optical fiber or awaveguide. The data is suitable for the transmission of high-speedsignals, for example, complying with serial advantage technologyattachment (SATA) standards and may be transmitted using wavelengthdivision multiplexing (WDM).

FIG. 15 is a block diagram of a module 600 including a plurality ofmemory devices 610-1 through 610-5 according to an exemplary embodimentof the inventive concept. One (e.g., 610-3) of the memory devices 610-1through 610-5 is directly connected to and communicates with a memorycontroller 620. The memory devices 610-1 through 610-5 may be seriallyconnected in a chain with one other. The memory devices 610-1, 610-2,610-4, and 610-5 that are not directly connected to the memorycontroller 620 communicate with a host indirectly through the chain.

In an exemplary embodiment, the memory controller 620 controlling theoperation of the memory devices 610-1 through 610-5 may implementedwithin the module 600 or may be stacked on the memory devices 610-1through 610-5.

FIG. 16 is a block diagram of a data processing system 800 including thememory device illustrated in FIG. 1 according to an exemplary embodimentof the inventive concept.

The data processing system 800 may be implemented as a personal computer(PC), a tablet PC, a net-book, an e-reader, a personal digital assistant(PDA), a portable multimedia player (PMP), an MP3 player, or an MP4player.

The data processing system 800 includes the memory device 840 and amemory controller 850 controlling the data processing operations of thememory device 840.

The memory controller 850 may correspond to the memory controller 100,100 a or 100 b according to an exemplary embodiment of the inventiveconcept, and the memory device 840 may correspond to the memory device200, 200 a, or 200 b according to an exemplary embodiment of theinventive concept

A processor 820 may display data stored in the memory device 840 througha display 810 according to data input through an input device 830. Theinput device 830 may be implemented by a pointing device such as a touchpad or a computer mouse, a keypad, or a keyboard.

The processor 820 may control the overall operation of the dataprocessing system 800 and the operations of the memory controller 850.

FIG. 17 is a block diagram of a data processing system 900 including thememory device 950 illustrated in FIG. 1 according to an exemplaryembodiment of the inventive concept. Referring to FIG. 17, the dataprocessing system 900 may be implemented as a cellular phone, a smartphone, a tablet personal computer (PC), a personal digital assistant(PDA) or a radio communication system.

The data processing system 900 includes the memory device 950 and amemory controller 960 controlling the operations of the memory device950. The memory controller 960 may control the data access operations,e.g., a write operation, and a read operation, of the memory device 950according to the control of a processor 940.

The data stored in the memory device 950 may be displayed through adisplay 930 according to the control of the processor 940 and/or thememory controller 960.

A radio transceiver 910 transmits or receives radio signals through anantenna ANT. The radio transceiver 910 may convert radio signalsreceived through the antenna ANT into signals that are processed by theprocessor 940. Accordingly, the processor 940 may process the signalsoutput from the radio transceiver 910 and may transmit the processedsignals to the memory controller 960 or the display 930. The memorycontroller 960 may transmit the signals processed by the processor 940to the memory device 950. The radio transceiver 910 may also convertsignals output from the processor 940 into radio signals and may outputthe radio signals to an external device through the antenna ANT.

An input device 920 enables control signals for controlling theoperation of the processor 940 or data to be processed by the processor940 to be input to the data processing system 900. The input device 920may be implemented by a pointing device such as a touch pad or acomputer mouse, a keypad, or a keyboard.

The processor 940 may control the operation of the display 930 todisplay data output from the memory controller 960, data output from theradio transceiver 910, or data output from the input device 920.

The memory controller 960 may correspond to the memory controller 100,100 a or 100 b according to an exemplary embodiment of the inventiveconcept, and the memory device 950 may correspond to the memory device200, 200 a, or 200 b according to an exemplary embodiment of theinventive concept.

FIG. 18 is a block diagram of a data processing system 1000 includingthe memory device illustrated in FIG. 1 according to an exemplaryembodiment of the inventive concept. The data processing system 1000 maybe implemented as an image processor such as a digital camera, acellular phone equipped with a digital camera, a smart phone equippedwith a digital camera, or a tablet PC equipped with a digital camera.

The data processing system 1000 includes the memory device 1040 and amemory controller 1050 controlling the data processing operations, suchas a write operation, and a read operation, of the memory device 1040.An image sensor 1010 included in the data processing system 1000converts optical images into digital signals and outputs the digitalsignals to a processor 1020 or the memory controller 1050. The digitalsignals may be controlled by the processor 1020 to be displayed througha display 1030 or stored in the memory device 1040 through the memorycontroller 1050.

Data stored in the memory device 1040 may be displayed through thedisplay 1030 according to the control of the processor 1020 or thememory controller 1050. The memory controller 1050 may control theoperations of the memory device 1040. The memory controller 1050 maycorrespond to the memory controller 100, 100 a or 100 b according to anexemplary embodiment of the inventive concept, and the memory device1040 may correspond to the memory device 200, 200 a, or 200 b accordingto an exemplary embodiment of the inventive concept.

FIG. 19 is a diagram of a multi-chip package 1300 including thesemiconductor memory device illustrated in FIG. 1 according to anexemplary embodiment of the inventive concept. Referring to FIG. 19, themulti-chip package 1300 includes a plurality of semiconductor devices,e.g., first through third chips 1330, 1340, and 1350 which aresequentially stacked on a package substrate 1310. Each of thesemiconductor devices 1330 through 1350 may include a memory controllerand/or a semiconductor memory device according to an exemplaryembodiment. A through-silicon via (TSV) (not shown), a bonding wire (notshown), a bump (not shown), or a solder ball 1320 may be used toelectrically connect the semiconductor devices 1330 through 1350 withone other.

The first semiconductor device 1330 may include a logic device dieincluding an input/output interface and a memory controller and thesecond and third semiconductor devices 1340 and 1350 may include amemory device die. For example, the second and third semiconductordevices 1340 and 1350 may include a plurality of memory devices stackedon each other, and may include a memory cell array. In an exemplaryembodiment, a memory device of the second semiconductor device 1340 anda memory device of the third semiconductor device 1350 may be the sameor different types of memory.

Alternatively, each of the first through third semiconductor devices1330 through 1350 may include a memory controller. In an exemplaryembodiment, the memory controller may be on the same die as a memorycell array or may be on a different die than the memory cell array.

In an exemplary embodiment, the first semiconductor device 1330 mayinclude an optical interface. A memory controller may be positioned inthe first or second semiconductor device 1330 or 1340 and a memorydevice may be positioned in the second or third semiconductor device1340 or 1350. The memory device may be connected with the memorycontroller through a TSV.

The multi-chip package 1300 may be implemented using hybrid memory cube(HMC) in which a memory controller and a memory cell array die arestacked. When the HMC is used, the performance of memory devicesincreases due to the increase of bandwidth and the area of the memorydevices is minimized. As a result, power consumption and manufacturingcost may be reduced.

FIG. 20 is an exemplary three-dimensional conceptual diagram of anexample of the multi-chip package 1300 illustrated in FIG. 19 accordingto an exemplary embodiment of the inventive concept. Referring to FIG.20, the multi-chip package 1300′ includes a plurality of the dies 1330through 1350 connected with one another through TSVs 1360 in a stackstructure. Each of the dies 1330 through 1350 may include a plurality ofcircuit blocks (not shown) and a periphery circuit to realize thefunctions of the semiconductor memory device 200. The dies 1330 through1350 may be referred to as a cell array. The plurality of circuit blocksmay be implemented by memory blocks.

The TSVs 1360 may include a conductive material including a metal suchas copper (Cu). The TSVs 1360 are arranged at the center of a siliconsubstrate. The silicon substrate surrounds the TSVs 1360. An insulatingregion (not shown) may be disposed between the TSVs 1360 and the siliconsubstrate.

The present general inventive concept can also be embodied ascomputer-readable codes on a computer-readable medium. Thecomputer-readable recording medium is any data storage device that canstore data as a program which can be thereafter read by a computersystem. Examples of the computer-readable recording medium includeread-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetictapes, floppy disks, and optical data storage devices.

The computer-readable recording medium can also be distributed overnetwork coupled computer systems so that the computer-readable code isstored and executed in a distributed fashion. Also, functional programs,codes, and code segments to accomplish the present general inventiveconcept can be easily construed by programmers.

As described above, according to an exemplary embodiment of theinventive concept, when a write operation of data is not properlyperformed in a memory device, a rewrite operation of the data isperformed, so that write fail problems are prevented.

Therefore, the probability of write fail in the fine processes of memorydevices is reduced. In addition, parameters, such as write recoverytime, of memory devices (e.g., DRAM) may be efficiently released, sothat the yield of memory devices can be increased with the releasedparameters.

While the present inventive concept has been shown and described withreference to exemplary embodiments thereof, it will be apparent to thoseof ordinary skill in the art that various changes in form and detail maybe made therein without departing from the sprit and scope of theinventive concept as defined by the following claims.

What is claimed is:
 1. A method of writing data to a memory device, themethod comprising: receiving a plurality of write requests and aplurality of data sets from a host; generating a plurality of writecommands and storing the plurality of write commands to a write queue;applying the plurality of write commands to a memory device between anactive command and a precharge command based on a predeterminedscheduling method; and applying a last write command of the plurality ofwrite commands to the memory device after the precharge command isperformed.
 2. The method of claim 1, further comprising: executing atleast one read command or at least one write command after applying theprecharge command and before applying the last write command.
 3. Themethod of claim 2, wherein the predetermined scheduling methoddetermines a priority among the plurality of write commands based on abank address and a row address.
 4. The method of claim 1, furthercomprising: removing a write command executed from the plurality ofwrite command stored in the write queue, wherein the last write commandis retained after the precharge command and is executed after theprecharge command.
 5. A memory controller, comprising: an arbiterconfigured to generate an active command, a precharge command, and aplurality of write commands and configured to issue the plurality ofwrite commands between the active command and the precharge command,wherein the precharge command is issued after a first write operation isperformed in response to a last write command of the plurality of writecommands , the last write command is issued for a second write operationafter the precharge command, and wherein the first write operation andthe second write operation write a same data set to memory cells ofplurality of memory cells.
 6. The memory controller of claim 5, furthercomprising: a write queue configured to store the plurality of writecommands.
 7. The memory controller of claim 5, wherein the data setinclude a number of data corresponding to a burst length.
 8. The memorysystem of claim 6, wherein the arbiter further configured to: receive aplurality of write requests from a host; generate the active command,the plurality of write commands, and the precharge command; store theplurality of write commands in the write queue; and schedule thecommands stored in the write queue according to a predeterminedscheduling algorithm.